Design-Reuse

The Quantum Race: Finding Europe s Formula 1

Quantum technologies are rapidly reshaping the frontiers of computing, communication, and sensing—areas with implications far beyond the laboratory. As nations and industries race to secure leadership ...
Design And Reuse

Dnotitia Releases "Dnotitia NIAH," an Open-Source Benchmark for Long-Context LLM Performance

October 2nd, 2025] Dnotitia Inc. (Dnotitia), a leader in long-term memory AI and semiconductor-integrated solutions, today announced the open-source release of Dnotitia NIAH(Needles in a Haystack) on ...
Design And Reuse

Photonics leaders call for a €2 bn EU program to 'keep Europe competitive'

The Position Paper sets out a program to “keep Europe in the game,” according to Photonics21. At its core is the €2 billion stand-alone photonics program in the next MFF, designed to crowd in €6–8 ...
Design And Reuse

Synopsys Introduces Digital Twin Racetrack and NVIDIA Omniverse to STEM Racing

Ansys, part of Synopsys, created a digital twin racetrack for STEM Racing (formerly F1 in Schools) that enables students to virtually test aerodynamics of miniature F1 cars using advanced ...
Design-Reuse

Keysight Unveils 3GPP AI Simulation Platform to Accelerate AI-enabled 6G Communications

Keysight Technologies, Inc. (NYSE: KEYS) today announced the release of WirelessPro 3GPP AI Simulation Platform (WirelessPro), a next-generation software platform designed to meet the evolving needs ...
Design And Reuse

Synopsys Gives Its Major EDA Offerings a Gen-AI Facelift

Synopsys recently expanded its EDA portfolio, highlighting new capabilities in its Synopsys.ai Copilot GenAI technology and extended integration with Ansys simulation tools. The update brings enhanced ...
Design And Reuse

Alphawave Semi Delivers Cutting-Edge UCIe Chiplet IP on TSMC 3DFabric Platform

Alphawave Semi’s UCIe-3D 5nm bottom die supports TSVs to supply power and ground to the 3nm top die. The company’s 3DIO portfolio also includes a proprietary design flow and methodology for fast and ...
Design And Reuse

Codasip RISC-V processors certified up to ASIL-D

The L735 and L739 were developed using Codasip’s IP development process, which has been certified as compliant to both ISO 26262 and ISO/SAE 21434 by TÜV SÜD. This foundation ensures that Codasip’s ...
Design-Reuse

Key ASIC Berhad Signs RM1.11 Million Contract to Jointly Develop AI-Driven, Ultra-Low Power RF Navigation Chip with Middle East Partner

Key ASIC Berhad (“Key ASIC” or “the Company”), a leader in ASIC design and innovation, has signed a contract worth RM1.11 million with a navigation systems company in the Middle East to jointly ...
Design And Reuse

Analogue Insight IP Group Launches Analogue Insight SAFE in Portland, Oregon to Deliver Certification-Grade Security IP for Next-Gen SoCs and Chiplets.

Analogue Insight SAFE LLC is the Group’s U.S. venture based in Oregon, focused on security IP for SoCs and chiplets. SAFE combines rigorous security architecture with integration-ready deliverables ...
Design And Reuse

Northern Poland Emerging as Europe's Next Semiconductor Hub

Our ambition is clear: to establish Pomerania as a next-generation European hub for semiconductor design, R&D, and advanced manufacturing. We see ourselves as part of a larger global network that ...