Semiconductor design is rapidly evolving because technologies such as AI and machine learning (ML) applications push the boundaries of complexity and specialization. Modern chips require hundreds or ...

Current work on adding AI to enhance EDA tools centers on copilots. Present and future ideas focus on letting engineers do much more with the same or fewer resources.

A novel PHY may be the answer to the packaging question.

Minimize the number of wires between dies with networking technology that allows data to move in both directions at the same time.

“Innovative fracturing techniques allow next-generation extraction tools offer accurate resistance extraction for various design scenarios, ensuring reliable performance and efficiency in IC designs.” ...

EDA tool providers will serve as a powerful ally for customers to develop and implement workflows, and to show them what's ...

New security technical papers presented at the August 2024 USENIX Security Symposium.

Context-aware SPICE simulation leverages the reliability verification tool’s knowledge of specific circuit topologies along with the layout geometries to retain only the portion of the design that is ...

More attack points and more valuable data are driving new approaches and regulations. The diversity of connected devices and chips at the edge — the vaguely defined middle ground between the end point ...

The generative AI market is experiencing rapid growth, driven by the increasing parameter size of Large Language Models (LLMs). This growth is pushing the boundaries of performance requirements for ...

The industry may have started with the wrong approach for enabling a third-party chiplet ecosystem, but who will step in and fix it?

This technology enhances overall design effectiveness by ensuring data flows smoothly and efficiently between the numerous IP blocks within a chip. FlexNoC 5 is designed to meet the demands of ...