Semiconductor Engineering

Raising The IP Abstraction Level

An increasing reliance on commercial and re-used IP and more emphasis placed on software development is adding even more pressure onto semiconductor design teams to figure out the benefits and ...
Design-Reuse

Creating IP level test cases which can be reused at SoC level

We are in an era where time is very important for product delivery. For processor based SoC, we invest lot of time in creating test cases which could have been simply reused from IP level verification ...
Design-Reuse

Automation in IP based SoC development: Case study of a media processor subsystem

An IP based development methodology for building system-on-a-chip solution is described. The methodology is illustrated through a memory centric SoC architecture template intended for streaming data ...
Business Wire

Cadence Brings Verification IP to the Chip Level with New System VIP Solution

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Cadence ® System-Level Verification IP (System VIP), a new suite of tools and libraries for automating ...
Semiconductor Engineering

Using Automotive IP For Easier Integration Of Safety Into SoCs

Today’s SoCs for automotive safety-related systems integrate numerous IP blocks. At the system level, the Hardware Software Interface (HSI) between these IP blocks needs to be verified in simulation ...